The present invention relates to a signal processor at the recording and the reproduction which is applicable to an external memory of a computer or the like, and more particularly, to that which increases the efficiency of an access to the memory.
A description will be given of a signal processing LSI including a memory such as a CD-ROM, with reference to FIGS. 5 and 6. In FIG. 5, numeral 11 denotes a recording medium such as a CD-ROM, numeral 12 denotes a buffer memory for storing data, numeral 13 denotes a host computer, numeral 14 denotes a decoder block which takes in data from the recording medium 11, numeral 15 denotes a memory control block which arbitrates memory access requests from respective blocks to perform a memory access, numeral 16 denotes an error correction block which performs error correction when there is an error in the data stored in the buffer memory 12, numeral 17 denotes a host I/F block for transferring data stored in the buffer memory 12 to the host computer 13, numeral 18 denotes a data bus of 16 bit width between blocks for transferring data between respective blocks and the memory control block 15, and numeral 19 denotes a memory data bus of 16 bit width for transferring data between the buffer memory 12 and the memory control block 15.
Next, a signal processing will be described by focusing on a buffering processing of the transfer from the recording medium 11 to the buffer memory 12, an error correction processing, and a host transfer processing of data after correction.
(1) Buffering Processing
In the recording medium 11, CD-ROM data are recorded in an interleaved manner in a prescribed data unit. A frame is composed of data of 1176 words (word=16 bits), and the data read from the recording medium 11 are inputted to the decoder block 14 as serial data. In the decoder block 14, a frame synchronizing signal is detected and a serial/parallel conversion is performed, and thereafter, data of 1170 words excluding the frame synchronizing signal are transferred to the memory control block 15 through the data bus 18 between blocks of 16 bit width. The memory control block 15 writes the received data into the buffer memory 12 through the memory data bus 19 of 16-bit width.
(2) Error Correction Processing
After data for one frame are stored in the buffer memory 12, the error correction block 16 accesses the buffer memory 12 through the data bus 18 between blocks, the memory control block 15, and the memory data bus 19, thereby to perform an error correction processing for one frame.
(3) Host Transfer Processing
After the error correction processing for data of at least one frame is completed, the host I/F block 17 reads data through the memory data bus 19, the memory control block 15, and the data bus 18 between blocks, and transfers the data to the host computer 13.
Since the above-described buffering, error correction, and host transfer are processed by pipeline control as depicted in FIGS. 6(a), (b), (c), respectively, the buffering and the error correction processing are required to complete processings for one frame within 1-frame time. However, the host transfer does not necessarily require processing for one frame to be completed within 1-frame time, and figure 6(c) shows that in case of host transfer, transfer of data for a corresponding frame is possible at a timing described therein.
FIG. 4 shows a logical format for a CD-ROM and illustrates the configuration of data for one frame excluding the frame synchronizing signal, and further, in the CD-ROM, data of 2340 bytes out of 2352 bytes of one frame, excluding the frame synchronizing signal of 6xc3x972 bytes, are divided into ones of even numbers and ones of odd numbers, so as to perform an error correction processing for respectively independent groups of 1170-byte data.
In FIG. 4, data of 2340 bytes for one frame are shown correspondingly to word numbers (1 word =16 bits) of 0 to 1169. In a CD-ROM, error correcting codes of P parity and Q parity are added, and the error correction processing employing P parity is performed employing data with intervals of 43 words such as 0th word, 43rd word, . . . , while the error correction processing employing Q parity is performed employing data with intervals of 44 words such as 0th word, 44th word, . . . , as shown in FIG. 4.
As described above, when attempting to improve the processing speed of error correction employing a conventional signal processor by extending the width of the memory data bus of the buffer memory 12, there is a problem such that it is not possible to perform a memory access for error correction efficiently by the conventional method of storing data to the buffer memory 12.
More particularly, when it is considered that the processing speed of error correction is enhanced by extending the width of the memory data bus of the buffer memory 12, when data read from the recording medium 11 is stored into the buffer memory 12 in order, that is, when storing is performed according to the logical format of a CD-ROM in FIG. 4, a memory access for error correction can not be performed efficiently in a case where the width of the memory data bus of the buffer memory 12 is over 16 bits such as, for example, when it is 64 bits.
With reference to FIG. 4, in case of error correction employing P parity, data of 64 bits in total are read in the order of word numbers 0000 and 0001 initially, and word numbers 0042 and 0043 subsequently, by an access to the buffer memory 12 by 32-bit bus 18. However, since data with intervals of 43 words are used for calculation and thereby, data of word numbers 0000 and 0043 only are calculated, 32-bit data of word numbers 0001 and 0042 are not used. Similarly, at the error correction employing Q parity, data of 64 bits in total are read in the order of word numbers 0000 and 0001 initially, and word numbers 0044 and 0045 subsequently, and data with intervals of 44 words are used for calculation, and therefore, data of word numbers 0000 and 0044 only are processed, and 32-bit data of word numbers 0001 and 0045 are not used.
According to a first aspect of the present invention, there is provided a signal processor which performs an access from plural blocks toward a buffer memory connected to a memory data bus having the first bus width through a memory control block, so as to perform reading of data, the signal processor comprising: a memory control block which performs writing of data into the buffer memory and reading of data stored in the buffer memory from the buffer memory through the memory data bus; and a data bus among blocks which has the second bus width narrower than that of the first bus width, and which transfers the data among the plural blocks and the memory control block; wherein the memory control block relocates data on the memory data bus to the data bus among blocks when performing reading of data from the buffer memory, and relocates data on the data bus among blocks to the memory data bus when performing writing of data into the buffer memory. Therefore, the number of memory access is reduced and a fast access is performed toward the buffer memory, whereby it is possible to increase the efficiency of the memory access as well as to downsize a circuit.
According to a second aspect of the present invention, the signal processor of the first aspect further comprises: an error correction block which is connected to the buffer memory through the memory control block, and which performs error correction processings of data for at least two frames which are stored in the buffer memory at the same time. Therefore, data for plural frames stored in the buffer memory are subjected to the error correction processing at the same time, thereby reducing unnecessary memory access.
According to a third aspect of the present invention, there is provided a signal processor of the first aspect, in which the memory control block, when storing data of successive N frames comprising prescribed word numbers into the buffer memory from a recording medium, stores first frame data into the buffer memory at intervals of Nxe2x88x921 word, stores second frame data at intervals of Nxe2x88x921 word so as to adjoin the first frame data, and stores the rest of Nth frame data subsequently at intervals of Nxe2x88x921 word so as to adjoin Nxe2x88x921th frame data, and N pieces of word data of different frames are stored successively in the buffer memory. Therefore, the width of the bus to the buffer memory is extended to reduce the number of memory access, whereby it is possible to increase the efficiency of an access to the buffer memory.